presentation
IBM introduced the POWER4 systems in 2001. POWER4 systems have incorporated many features previously included only in mainframe systems. POWER4 chip integrates onto a single die two processor cores, a shared second-level cache and the circuitry necessary to interconnect it directly with other POWER4 chips to form a system.
A high-instruction-level parallelism was achieved through a specific architecture design for the execution of instruction.
The POWER5 chip is the next-generation chip. The principal changes are support for Simultaneous multithreading (SMT) and an on-die memory controller. Each core of the supports 2 threads. A power 5 CPU is made of 2 core. We have then 4 threads. With a power 5+ you can reach 4 cores.
The multithreading of the CPU can be activated or not, through AIX commands. These commands are dynamics, and can stay after the next reboot.
utilisation
To look at the actual state type:
#smtctl This system is SMT capable. SMT is currently enabled. SMT boot mode is not set. SMT threads are bound to the same physical processor. proc0 has 2 SMT threads. Bind processor 0 is bound with proc0 Bind processor 1 is bound with proc0 proc2 has 2 SMT threads. Bind processor 2 is bound with proc2 Bind processor 3 is bound with proc2 |
If the system can stand SMT, you would get this message:
smtctl: SMT is not supported on this system. |
To change the status of SMT to on just type:
smtctl -m 'on' |
To switch back for having only one thread by core:
smtctl -m 'off' |
You can also add the option -w now if you don't want the system to remain the state after the next reboot.
Don't forget to change the bosboot image if you change the this option at reboot, and type
bosboot -a. |